Відео

ppts of the last time I taught are on this dropbox link: tinyurl.com/aca-2020

Not that I know of. And not on this channel

Now that you have said that, I am also surprised. It gets better after around 20 mins. But the same content is covered in another playlist too. You can watch it here ua-cam.com/video/Q4HDAAXBUns/v-deo.html Either this or next video will cover the same topic.

@@RenzymEducation yes it got better. yes i did jumped to that video thanks!

@@RenzymEducation no its the next video. i'll share link just for the convenience of others. ua-cam.com/video/b5_92s6K8cU/v-deo.html

Thanks a lot Mustahsan.

Men samjha nahi. You mean why I haven't uploaded new videos for some time?

@@RenzymEducation yes

I have taken a break from teaching courses, but I am thinking of uploading videos whenever I find time.

Its Abasyn University Islamabad

Thanks Iffat. I am glad that it helped.

Thanks. That would be great ;)

I don't have lab material with me , but I did upload sample assignments and slides for this course on this dropbox link: tinyurl.com/DSD-Shoab

Also since this Verilog topic is common between Digital logic design and Digital system design, the slides and sample assignments related to logic design can be found at this dropbox link instead: tinyurl.com/dld-slides

Saag da maza te real ich aa, virtual ich te munh ich pani ana ae bas

Thanks Jhujhar. I am glad it helped

@@RenzymEducation thanks to you Paji. Keep on your good stuff and I love your Urdu/ Punjabi language and your content. It's easy to remember and more sticky.

@@RenzymEducation can you please make more videos on PCB design, bigger verilog design projects and may be live coding.

@@jujharuiet PCB design is not my field directly but I want to do videos on bigger Verilog designs but am unable to find bandwidth to do that. If it happens, it would be at least after a few months

@@RenzymEducation looking forward eagerly to that day. My best wishes and warm hugs 🤗.

Typically Pmod boards come with example code and that could be a good starting point e.g. here is Digilent's guide about Pmod IPs digilent.com/reference/learn/programmable-logic/tutorials/pmod-ips/start

@@RenzymEducationI couldn't find these IPs in my IP catalog maybe my board doesn't support them. But still, it should be possible to use them without using IPs.

The article mentions that the support is till Vivado 2019.1 or earlier. So if your version is higher, you might not be able to use the IPs. Secondly I assume that you have followed all the steps, step 2 in particular and have downloaded the IP from Github and followed the steps to add it to repos. Yes, without the IP you should still be able to connect the Pmod pins in the XDC file and use those in your design

Pakistan

Writes generally complete in one cycle. Reads can take two cycles. But even in that case you can issue address on each cycle i.e. you will have two cycles latency on each write, but can read on every cycle

Yes. The link to slides and codes is given in the first video of the playlist. Here it is again tinyurl.com/dld-slides

These lectures were given at Abasyn University Islamabad

Thanks Sajjan

Thanks Ranjeet. I am glad it helped.

Thanks a lot

A little bit complex design example (in English) is that of a small processor ua-cam.com/video/HCzIK322Pzw/v-deo.html

@@RenzymEducation too many steps ) but ill check. Thanks

Yasir

For RAW, we need to compare CURRENT instruction's sources against PREVIOUS instruction's destinations. PREVIOUS instruction's sources are not required for RAW.

Link to slides is there in the video description

@@RenzymEducation but sir slides url redirect to empty page

@@zainbhatti5565 Thanks for pointing out. I have updated it and it should work now. Also the link in description is of 2012 offering. If you want to see slides of latest offering at Berkley. Use this link inst.eecs.berkeley.edu/~cs152/sp23/ It also has link to Berkley lecture videos as well if you prefer learning directly from there

Thanks Sir. You help alot. God bless you@@RenzymEducation

Yes BRAM has an output register that we can not remove. But our design (so far) is a single cycle design where we expect that whatever is loaded comes out of BRAM in the same cycle. BRAM will instead be giving out data of whatever address was there on the last cycle. To cover that up, we can issue load instruction twice. First one will load incorrect data but in 2nd cycle correct data of first load will come out and since same load instruction is issued so it will be correctly stored

Thanks a lot